1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor memory device calibration method and, more particularly, to a double data rate synchronous dynamic random access memory (DDR SDRAM) and a calibration method therefor.
2. Discussion of the Related Art
Double Data Rate (DDR) memory devices use source synchronous transfers when data is written to or read from the memory devices. The data strobe signal (DQS) is sent along with the data (DQ) to be clocked to a memory controller. The DQS signal is edge-aligned with the DQ signal for read cycles and center-aligned with the DQ signal for write cycles.
Second generation Double Data Rate (DDR-II) devices as defined by JEDEC Solid State Technology Association Standard JESD90 conform to the Series Stub Terminated Logic for 1.8 volt operation (SSTL—1.8) signaling level standard as defined by JEDEC Standard JESD8-15. The SSTL—1.8 standard has been developed to ensure that the data signals can meet the higher data throughputs speeds needed for newer memory systems. SSTL—1.8 is optimized for the memory environment, though it can be used in other situations. The primary benefits of the SSTL—1.8 signaling method are its ability to drive many stub terminated loads, reduce signal voltage swings, ensure compatibility with newer memory products, and reduce EMI/RFI.
Referring to FIG. 1, the output buffer is essentially a standard P-channel/N-channel CMOS driver 110 operating at the lower 1.8 v VDDQ 120. The key difference of the SSTL—1.8 circuits is the use of a reference voltage VREF 102 that serves as an input to a reference potential input terminal of a typical input receiver 100. VREF 102 provides a reference for determining whether an input signal is a high level signal or a low level signal. The typical input receiver 100 includes a differential pair common source amplifier. One input to the differential amplifier is the incoming data signal 101 and the other input is the reference voltage VREF 102. The reference voltage 102 is shared between all memory devices and a memory controller. This type of receiver has the advantage of rejecting common mode noise while providing better gain, higher bandwidth, and a reducing threshold offset due to proximity and size of the transistor differential pair as compared to the standard transistor-transistor logic (TTL) type of receiver. This results in improved signal swing sensitivity and reliability, and also higher operating speeds.
The SSTL—1.8 signaling standard is built upon the idea of transmitting data at a different level versus the older logic level swing. The standard has the data bit swinging around the midpoint of the data bus's supply level. Because the data signals are single ended the reference voltage must track the midpoint of the signal transitions. VREF must be kept within 2% of the midpoint of the signal voltage swing. To consume reasonable power, high frequency signaling requires small amplitude signals. For a receiver to detect small voltage swings e.g., 0.5 volts easily in a noisy environment, the current must also be very large (e.g., on the order of 50 to 60 milliamps per driver). With this differential structure, the difference between VIH and VIL may be 0.5 volts (0.25 volts from the midpoint) vs. the 1.2 volt swing (VIH=2.0 volts and VIL=0.8 volts) found on LVTTL (Low Voltage TTL). VREF is defined as 0.5 of VDDQ (bus supply), and VSSQ is at ground. VREF must track VDDQ in order to ensure proper detection by the input receivers.
The VREF signal is a high impedance DC voltage reference generated from, and which tracks with, the power supply over time, but cannot respond to instantaneous noise. Usually, the DC value of the power supply varies by five percent (5%). FIG. 2 is a timing diagram illustrating an example signal 201 relative to a VREF 102, high reference voltage (VREFH) 203 and a low reference voltage (VREFL) 204. The VREFH 203 and VREFL 204 values typically depend on power supply variation used to generate the VREF 102 signal. The large voltage swing, i.e., the difference between a high voltage signal (VIH) 210 and a low voltage signal (VIL) 211, and stable signal levels above and below the VREF 102 signal are required for reliable detection of signal state. The DDR-II volatage swing is approximately 1.2 volts.
In order to achieve a data signal that swings symmetrically around 0.5 of VDDQ, the pull-up and pull-down Ron resistance of the P-channel/N-channel drivers must be closely matched through a calibration procedure. The P-channel/N-channel CMOS driver actually consists of a number of parallel P-channel pull-up “legs” and a number of parallel N-channel pull-down “legs”. The pull-up or pull-down Ron resistance is inversely proportional to the driver strength, i.e., the number of parallel driver legs that are driven on. In addition, the calibration of the pull-up and pull-down Ron resistance of the P-channel/N-channel drivers should be made with the drivers operating in their linear region.
Therefore, what is needed is a calibration procedure that matches the P-channel/N-channel pull-up/pull-down Ron and also calibrates the P-channel/N-channel pull-up/pull-down drivers in their linear region of operation.